1. The Field of the Invention
The present invention relates to methods for manufacturing semiconductor devices. More particularly, the present invention relates to a method for fabricating a semiconductor device, such as a capacitor, utilizing high temperature alloys to stabilize rugged polysilicon grains on the device.
2. The Relevant Technology
As integrated circuit technology has progressed, it has become possible to store ever-increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly and reliably. Central to this increased ability to store and retrieve data has been the dynamic random access memory (DRAM), fabricated as an integrated circuit. The memory cells of DRAMs are comprised of two main components, a transistor and a capacitor. The capacitor of each memory cell functions to store an electrical charge representing a digital value (e.g., a charged capacitor representing a 1 and a discharged capacitor representing a 0) with the transistor acting as a switch to connect the capacitor to the "outside world" via decoding and other circuitry. In order to function properly, the capacitor must possess a minimum amount of capacitance. If a capacitor exhibits too little capacitance, it will cause errors in data storage.
Various approaches have been developed to increase the capacitance of a capacitor element in a memory cell of a DRAM device. For example, U.S. Pat. No. 5,352,623 to Kamiyama discloses a method in which a thin film of tantalum oxide is formed as a dielectric layer in a capacitor element. Prior to forming the tantalum oxide film, it is necessary to perform a separate step in order to remove a natural oxide film from the surface of a polysilicon layer forming a lower electrode of the capacitor element.
The capacitive value of a capacitor is dependent upon the dielectric constant of the material placed between the plates of the capacitor, the distance between the plates, and the effective area of the plates. In the case of integrated circuits, the material used as a dielectric between the plates is generally limited to only a few materials. Also, the minimum distance between the capacitor plates is generally limited to a particular value; once that value is exceeded, the occurrence of defects becomes unacceptably high. Thus, the one parameter that can be varied to obtain an increased storage capacity is the area of the plates. Accordingly, capacitance increases have also been achieved for a given dielectric thickness and for a given capacitor footprint area through an increase in the surface area of the capacitor.
A material that has been used to increase the surface area of capacitor plates and thereby cell capacitance is rugged polysilicon, which is a granular, rough material deposited in the capacitor module of DRAM cells as the lower plate below the dielectric layer. A drawback to the use of rugged polysilicon is that the conductive grains thereof can become detached from an underlying semiconductor substrate during subsequent processing and can redeposit between memory cells, causing electrical shorts or double bit failures of adjacent memory cells. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator and silicon-on-sapphire.
Much effort has been directed toward minimizing these electrical shorts, including dry etch recessing of the polysilicon grains, wet etch recessing of the polysilicon grains, and performing chemical/mechanical planarization (CMP) with a dry or wet recess of the polysilicon grains. Unfortunately, all of these techniques, while reducing double bit failures, also reduce capacitance in the capacitor element of a memory cell. Other methods of double bit failure reduction have focused on developing rugged polysilicon films with reduced roughness to provide for better adhesion to the underlying substrate. While these techniques reduce double bit failures, cell capacitance is reduced due to a loss in capacitor surface area.
Accordingly, there is a need for improved capacitor manufacturing methods that overcome or avoid the above problems.